The present invention relates to a semiconductor device which has a particularly fine contact structure and which has been subjected to a high-density integration, and a method of manufacturing the same.
In a semiconductor device, an element area or an interwire contact structure obtained by contact holes are further made fine, and accuracy and low resistance contributing to high reliability are required.
FIGS. 12A to 12F are sectional views for explaining a first conventional example showing a method of manufacturing of a contact-wire structure in the order of manufacturing processes. This technique is illustrated, for example, with reference to Jpn. Pat Appln. Publication No. 9-172067 or the like, and it is a technique for forming wire grooves and contact holes in a self-aligning manner.
As shown in FIG. 12A, a wire layer 701 is formed in advance on a insulation film 700 by using a well-known technique such as a damascene method or the like, and an insulation film 702 such as a silicon oxide film is deposited on the insulation film 700. Next, as shown in FIG. 12B, an insulation film 703 different in etching rate from the insulation film 702, for example, a silicon nitride film or the like, is thin deposited on the insulation film 702.
Next, as shown in FIG. 12C, opening portions 704 are formed on the insulation film 703 by using a photolithography technique and an etching technique. Next, as shown in FIG. 12D, an insulation film 705 different in etching rate from the insulation film 703, for example the same silicon oxide film as the insulation film 702 or the like, is further deposited on the insulation film 703.
Next, as shown in FIG. 12E, wire grooves 706 are formed on the insulation film 705 by using a lithography technique and an anisotropic selective etching technique. At this time, portions of the insulation film 702 corresponding to overlapping portions of a wire groove pattern and the opening portions 704 are also etched. Thereby, contact holes 707 are also formed simultaneously with formation of the wire grooves 706. That is, it is possible to form the wire grooves 706 and the contact holes 707 in a self-aligning manner.
Next, as shown in FIG. 12F, conductive material 708 is embedded in the wire grooves 706 and the contact holes 707, and projecting portions of the conductive material 708 are removed by using, for example, CMP (Chemical Mechanical Polishing) so that the conductive material 708 is flattened. Thereby, contact plugs 710 and wire layers 709 are formed.
According to the above configuration, contact hole positions are determined at overlapping portions of the opening portions 704 and the wire grooves 706. When each wire groove 706 is formed wider in the vicinity of each contact hole position to securely accommodate each opening portion 704 at a time of formation of the wire grooves 706, a problem of misalignment between the wire groove 706 and the contact hole 707 can be overcome.
Also, when there is an extra area in a contact area of the lowermost layer to some extent, the opening portion 704 may be formed wider in the vicinity of the contact hole position at least in a direction intersecting the wire groove 706. The opening portion 704 can securely be accommodated in the wire groove 706 at a time of formation of the wire groove 706 so that the problem of misalignment between the wire groove 706 and the contact hole 707 can be overcome.
However, according to the first conventional example, the wire groove 706 and the contact hole 707 are formed by using an anisotropic selective etching technique. For this reason, side walls of the contact hole 707 are formed approximately vertically to a semiconductor substrate face.
FIGS. 13, 14A, 14B, 15, 16A and 16B are views showing problems regarding such a manufacturing method as the above first conventional example. FIG. 13 is a plan view showing wire grooves and a contact hole, FIGS. 14A and 14B are sectional views taken along line XIVAxe2x80x94XIVA and XIVBxe2x80x94XIVB, respectively, and FIG. 15 is a sectional view showing an aspect where conductive material is embedded in the contact hole in the sectional view of FIG. 14A. FIGS. 16A and 16B are respectively sectional views corresponding to FIGS. 14A and 14B, for showing a modified example. Same reference numerals are attached to portions similar to the first conventional example shown in FIGS. 12A to 12F.
In FIGS. 13, 14A and 14B, in an insulation film 703 defining a bottom portion of a wire groove, an opening portion 704 is formed wider in the vicinity of a contact hole position at least in a direction intersecting a wire groove 706. A contact hole 707 is etched approximately vertically to the bottom portion. It is difficult to embed barrier metal or conductive material 708 in such a contact hole 707 in a preferable manner.
As shown in FIG. 15, for example, there is a drawback in which a seam 711 and a void 712 may occur. The seam 711 prevents planarization in a grinding process performed later. It is hard to foresee adverse influence of gas in the void 712 in a heating process performed later.
In view of the above, it is considered to employ a taper etching technique as a method for embedding conductive material 708 in the contact hole 707 in a preferable manner. That is, a taper angle is provided to a side wall of the contact hole 707 by controlling etching conditions. Thereby, an embedding characteristic of the conductive material 708 embedded in the contact hole 707 is improved.
FIGS. 16A and 16B are sectional view corresponding to FIGS. 14A and 14B, where the taper etching technique is adopted. That is, FIGS. 16A and 16B show a structure obtained by employing the taper etching technique in order to form wire grooves 706 and contact holes 707 simultaneously.
As shown in FIG. 16A, in a section taken along a direction of the wire groove 706, a taper angle is provided to each contact hole side wall by a method using the taper etching technique so that improvement in embedding characteristic is expected. It should be noted that, when an area (an area contacting with conductive material) of a contact hole bottom face 715 is intended to be secured to some extent, an opening area at an upper portion of the contact hole 707 is larger than the area of the contact hole bottom face 715.
As shown in FIG. 16B, a section taken along a direction perpendicular to the wire groove 706 clearly illustrates a harmful influence due to using the taper etching technique. When the area (an area contacting with conductive material) of the contact hole bottom face 715 intended to be secured to some extent, the opening area of the upper portion of the contact hole 707 becomes larger than the area of the bottom face.
As mentioned above, as the contact holes 707 and the wire grooves 706 are simultaneously formed, all the wire grooves 706 are tapered. Accordingly, an interval between adjacent wire grooves 706 at their upper portions is made small, so that a possibility where a short-circuit may occur between wire layers is increased.
Namely, the wire groove 706 itself has an aspect ratio smaller than that of the contact hole portion, and the taper angle is not so required at the side wall of the wire groove. However, the side wall of the wire groove 706 is necessarily provided with a taper angle when the method for forming the wire grooves 706 and the contact holes 707 simultaneously is used. As shown with Db in FIG. 16B, a configuration where the adjacent wire grooves are unnecessarily close to each other prevents the wire region or area from being structured further fine.
On the other hand, attention is paid to the contact structure itself in the contact hole. As a fine structurization advances, contact resistance, reaction barrier performance and covering characteristic for serving as an embedded plug become important. A conventional example will be explained below.
In a semiconductor device, metal, for example, W (tungsten), Al (aluminum) or the like, is often used as a wire layer or a contact plug. There is a drawback that such metal for a contact plug reacts with a wire layer (including a silicon substrate and a poly-plug) which is an underlayer, which may result in junction failure.
Accordingly, barrier metal is often used as the contact plug. TiN (Titanium nitride) is given as a representative barrier metal. Assuming a contact metal to a Si substrate, it is common to form TiSi2 (Titanium Silicide) between the barrier metal TiN and the Si substrate in order to obtain a good contact resistance.
FIGS. 17A to 17C are sectional views for respectively explaining a second conventional example showing a method for manufacturing a contact plug in a Si substrate in the order of manufacturing processes. This example includes a step of forming a barrier metal of TiN using a sputtering method.
First, a contact hole 802 is formed in an insulation film 801 on a substrate 800 by using a lithography technique and an etching technique. Thereafter, Ti and TiN are sequentially deposited on the insulation film 801 and in the contact hole 802 by using a sputtering method (see FIG. 17A). Next, the Si substrate thus processed is annealed in nitrogen atmosphere, so that the Ti at the lower portion is changed to TiSi2 (see FIG. 17B). Then, W is embedded in the contact hole and an top face of the Si substrate is flattened (see FIG. 17C).
In this method, the TiN can be deposited in any thickness in order to increase a barrier performance. As shown in FIGS. 17B and 17C, however, covering characteristic deteriorates at an edge of a contact bottom portion in a deposition shape of TiN obtained by the sputtering method. At a portion 803 where the covering characteristic deteriorates, a barrier performance is also lowered. As a result, there occurs a drawback that yield or reliability may be lowered.
FIGS. 18A to 18C are sectional views for respectively explaining a third example showing a method for manufacturing a contact plug in a Si substrate in the order of manufacturing processes. This example includes a process where Ti deposited by a sputtering process is thermally nitrided to be changed to a barrier metal of TiN. In this example, same reference numerals denote the same portions as those in the second example.
First, a contact hole 802 is formed in an insulation film 801 on a substrate 800 by using a lithography technique and an etching technique. Thereafter, Ti is deposited on the insulation film 801 and in the contact hole 802 by using a sputtering process (see FIG. 18A). In this state, the substrate thus processed is annealed in nitrogen atmosphere. Thereby, a lower portion of the contact hole is changed to TiSi2 and an upper portion thereof except for the lower portion is thermally nitrided to be changed to TiN (see FIG. 18B). Then, W is embedded in the contact hole and a top portion thereof is flattened (see FIG. 18C).
In this method, a Ti film having more excellent covering characteristic than TiN is thermally nitrided. For this reason, TiN can be formed approximately uniformly even at an edge of a contact bottom portion. In the bottom portion of the contact hole 802, however, as the TiN film and the lower TiSi2 film are simultaneously formed, a ratio of the film thicknesses of the TiN film and the TiSi2 is determined according to the respective reaction rates of the TiN film and the TiSi2 film. That is, the distribution of the thicknesses of the TiN film and the TiSi2 film is necessarily determined according to a difference between two reaction rates of Tixe2x86x92TiN and Tixe2x86x92TiSi2, as shown by broken circle 804. Accordingly, the film thicknesses of the both could not have been optimized independently.
FIGS. 19A to 19C are sectional views for respectively explaining a fourth conventional example showing a method for manufacturing a contact plug to a Si substrate in the order of manufacturing processes. This example includes a deposition process of TiN according to CVD process. In this example, same reference numerals denote portions similar to those of the second conventional example.
First, a contact hole 802 is formed in an insulation film 801 on a substrate 800 by using lithography technique and etching technique. Next, Ti and TiN are deposited on the insulation film 801 by CVD process (see FIG. 19A). In this state, the substrate thus processed is annealed in nitrogen atmosphere. Thereby, Ti of the lower portion in the contact hole is changed to TiSi2 (see FIG. 19B). Thereafter, w is embedded in the contact hole, and the upper portion thereof is flattened (see FIG. 19C).
In this method, CVD-TiN having an excellent edge covering characteristic is used. Accordingly, an excellent barrier performance can be obtained even at an edge of the contact hole bottom portion. In the CVD process, however, Ti and TiN are deposited even on a side wall of the contact hole with the almost same thickness as that of the bottom portion. For this reason, there occurs a problem that a fine structurization proceeds so that the diameter of the contact hole becomes small.
That is, when TiN is not made sufficiently thick as compared with the minimum thickness film required to serve as a reaction barrier, the contact hole is almost filled with barrier metal, as shown by broken circle 805 in FIG. 19C. Therefore, it becomes difficult to embed metal having a resistance lower than that of the barrier metal, for example, W, Al, Cu or the like, in the contact hole later. Consequently, there occurs a problem that the resistance of the contact plug can not be reduced sufficiently.
In this manner, even when attention is paid to the contact plug structure, as the fine structurization advances, it becomes impossible for the conventional techniques to meet the contact resistance, the barrier performance and the metal embedding characteristic.
Conventionally, formation of contact holes using the taper etching technique has an advantage where an embedding shape of conductive material embedded thereafter becomes good. On the contrary, there occurs a problem that the upper portion (opening) of the contact hole becomes uniformly larger than the bottom portion thereof.
That is, when a contact area of the contact hole bottom portion is intended to be secured to some extent, a distance or interval between adjacent conductive portions, for example, adjacent wire grooves, becomes narrow. Therefore, there is a drawback in which, when conductive material is embedded in the above contact holes and wire grooves, adjacent wire layers which should originally be isolated may be short-circuited. A relationship between the wire grooves and the contact holes arranged at fine intervals causes a much serious problem.
Also, when attention is paid to the contact plug structure of the contact hole, it becomes difficult in the conventional techniques to form a structure where all the contact resistance, the reaction barrier performance and the metal embedding characteristic are made excellent, which result in necessity of further improvement.
In view of the above circumstances, a first object of the present invention is to provide a semiconductor device where contact holes are formed to wire grooves in a self-aligning manner and which has a structure having an excellent conductive material embedding characteristic while preventing wires from being short-circuited even when an interval between the wires is reduced, and a method of manufacturing the same.
A second object of the invention is to provide a method of manufacturing a semiconductor device which has a highly reliable contact plug structure where contact resistance, barrier performance and metal embedding characteristic are satisfied sufficiently even when the semiconductor device is made highly fine.
A semiconductor device according to a first aspect of the present invention comprising a first insulation film; a second insulation film formed on the first insulation film and having an opening portion; a third insulation film formed on the opening portion and the second insulation film; and a contact hole formed in the third insulation film and the first insulation film, wherein only the side wall portion conducted by the opening portion of a side wall of the contact hole is provided with a substantial taper angle.
The semiconductor device according to the first aspect of the present invention may further comprise a wiring groove formed in the third insulation film and on the second insulation film, wherein only a portion of a side wall of the contact hole, which is in the direction crossing the direction of the wiring groove, is provided with a substantial taper angle.
The semiconductor device according to the first aspect of the present invention may further comprise a second wiring groove formed in the third insulation film and on the second insulation film, wherein only a side wall of the side walls of the first wiring groove, which is in the direction crossing the direction of the second wiring groove, is provided with a substantial taper angle. The opening portion may cross a plurality of the second wiring grooves.
In the semiconductor device according to the first aspect of the present invention, the first wiring groove may cross a plurality of the opening portions.
In the semiconductor device according to the first aspect of the present invention, the etching rates of the first and third insulation films may be larger than that of the second insulation film under an appropriate etching condition.
A semiconductor device according to a second aspect of the present invention comprises a first insulation film; a second insulation film formed on the first insulation film and having an opening portion; a third insulation film formed on the opening portion and the second insulation film; and a contact hole formed in the third insulation film and the first insulation film, wherein a first taper angle formed on at least a portion of a side wall portion of the contact hole formed in the first insulation film is larger than a second taper angle of a side wall portion of the contact hole formed in the third insulation film.
A semiconductor device according to a third aspect of the present invention comprises a first insulation film; a second insulation film formed on the first insulation film and having an opening portion; a third insulation film formed on the opening portion and the second insulation film; a contact hole formed in the third insulation film and the first insulation film; and a wiring groove formed in the third insulation film and on the second insulation film, wherein a taper angle formed on a side wall portion of the contact hole is larger than a taper angle of a side wall of the wiring groove.
A semiconductor device according to a fourth aspect of the present invention comprises a transistor provided with a gate electrode formed on a semiconductor substrate and a source/drain region formed in the semiconductor substrate, close to the gate electrodes; a first insulation film deposited to cover the transistor; a second insulation film formed on the first insulation film and having an opening portion; a third insulation film formed on the opening portion and the second insulation film; and a contact hole formed in the third insulation film and the first insulation film and which is connected to the gate electrode or the source/drain region, wherein only a side wall portion of the contact hole is provided with a substantial taper angle.
A semiconductor device according to a fifth aspect of the present invention comprises a first insulation film formed on a semiconductor substrate; a second insulation film formed on the first insulation film, having an opening hole leading to a contact hole; and a third insulation film formed on the second insulation film, separating a wire groove, wherein the contact hole is formed in a region corresponding to a region where a bottom portion of the wire groove and the opening portion are in contact with each other, and a taper angle formed on at least one portion of a side wall of the contact hole is larger than a taper angle of a side wall of the wire groove.
A semiconductor device according to a fourth aspect of the present invention comprises a transistor provided with a gate electrode formed on a semiconductor substrate and a source/drain region formed in the semiconductor substrate, close to the gate electrodes; a first insulation film deposited to cover the transistor; a second insulation film formed on the first insulation film and having an opening portion; a third insulation film formed on the opening portion and the second insulation film; and a first wiring groove which is formed in the third insulation film and the first insulation film with at least a portion of the side wall of the first wiring groove being conducted by the opening portion and which is connected to the gate electrode or the source/drain region, wherein only the side wall portion of the side wall of the wiring groove, which is conducted by the opening portion, is provided with a substantial taper angle.
A semiconductor device according to a fifth aspect of the present invention comprises a first insulation film formed on a semiconductor substrate; a second insulation film formed on the first insulation film, having an opening hole leading to a contact hole; and a third insulation film formed on the second insulation film, separating a wire groove, wherein the contact hole is formed in a region corresponding to a region where a bottom portion of the wire groove and the opening portion are in contact with each other, and a taper angle formed at least one portion of a side wall of the contact hole is larger than a taper angle of a side wall of the wire groove.
A semiconductor device according to a sixth aspect of the present invention comprises a first insulation film formed on a semiconductor substrate; a second insulation film formed on the first insulation film, having a plurality of opening holes leading to contact holes; and a third insulation film formed on the second insulation film, separating a plurality of wire grooves, wherein each of the contact holes is formed in a region corresponding to a region where a bottom portion of a corresponding one of the wire grooves and a corresponding one of the opening holes are in contact with each other, and a substantial taper angle is provided on only a side wall of each of the contact holes along an edge of a corresponding one of the opening holes at a bottom portion of a corresponding one of the wire grooves.
A method of manufacturing a semiconductor device according to a seventh aspect of the present invention comprises the steps of depositing a first insulation film on a semiconductor substrate; depositing a second insulation film on the first insulation film; forming in the second insulation film an opening portion; depositing a third interlayer insulation film on the second interlayer insulation film and on portions of the first insulation film exposed by the opening portion; and etching the third insulation film and the first insulation film to form a wire groove on the third insulation film while the second insulation film is hardly etched, and to form a contact hole in the first insulation film with a substantial taper angle at a portion of a side wall of the contact hole while an edge portion of the opening portion exposed during the etching process is gradually removed, using an anisotropic selective etching technique having a slightly lower etching selectivity.
A method of manufacturing a semiconductor device according to an eighth aspect of the present invention, comprises the steps of forming a transistor provided with a gate electrode on a semiconductor substrate, and a source/region region in the semiconductor substrate, adjacent to the gate electrode; depositing a first insulation film over the transistor; depositing a second insulation film on the first insulation film; forming an opening portion in the second insulation film; depositing a third interlayer insulation film on the second interlayer insulation film and a portion of the first insulation film exposed by the opening hole; and etching the third insulation film and the first insulation film to form a wire groove on the third insulation film while the second insulation film is hardly etched, and to form in the first insulation film a contact hole leading to the gate electrode or the source/drain region of the transistor with a substantial taper angle at a portion of a side wall of the contact hole while an edge portion of the opening portion exposed during the etching process is gradually removed, using an anisotropic selective etching technique having a slightly lower etching selectivity.
A method of manufacturing a semiconductor device according to a ninth aspect of the present invention comprises the steps of forming an opening hole in an insulation film; depositing a first refractory metal film in the opening hole; nitrifying a surface of the first refractory metal film; depositing a second refractory metal film on a nitrified surface of the first refractory metal film; and changing the second refractory metal film to a nitride film by a thermal treatment.
A method of manufacturing a semiconductor device according to a tenth aspect of the present invention comprises the steps of forming an opening hole in an insulating film; depositing a first refractory metal film in the opening hole; depositing a refractory metal nitride film on a surface of the first refractory metal film; depositing a second refractory metal film on a surface of the refractory metal nitride film; and changing the second refractory metal film to a nitride film by heat treatment.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.